Integrated circuits (ICs) are widely used in virtually all electronic devices. Unfortunately, a given IC may have a sales lifetime in excess of ten years, while the manufacturing life of the IC is only about five years. A typical semiconductor manufacturing facility upgrades its fabrication lines to accommodate more advanced processes. For example, the ability to run larger wafers containing higher device densities may generate more revenue. Economics typically mean that a semiconductor manufacturer can recover upgrade costs more quickly by manufacturing the densest integrated circuits using the newest processes. Although older integrated circuits will often still be manufacturable on the upgraded line, the revenue generated will be less than that generated by higher density designs using the upgraded processes. Accordingly, certain older integrated circuits may become unavailable. Unfortunately, the unavailability of a single IC that is part of an overall electronic system may render the system difficult or impossible to manufacture until a replacement for the IC is developed.
There are several conventional approaches for developing and producing a replacement IC compatible with a newer semiconductor manufacturing process. One is to simply totally redesign the IC, and which may result in a superior IC. Unfortunately, a total redesign is a long process and may be relatively expensive.
Another approach is a manual redesign wherein the logic is moved from one library to another. This can be a time consuming task and the target library may not contain all of the logic functions used in the predecessor library. Moreover, the decisions made in the manual redesign relating to timing of altered logic may be incorrect, thereby introducing errors in the design. In addition, even if the target library includes matching cells, their delays will not necessarily ratio uniformly. Accordingly, exhaustive simulations may be required to ensure that the new part is acceptable. If security fault analysis (SFA) or certification is needed, the time period may be even further extended before the part is available.
Another approach is known as Netlist conversion using Computer Aided Engineering (CAE) software which is typically relatively expensive. Netlist conversion assumes that all cells used in the obsolete design are present in the target process. Netlist conversion may be more reliable than manual conversion; however, the new IC will have a different layout. The layout changes may result in logic elements being placed differently and interconnects being routed differently. Simulations need to be thorough and exhaustive to insure the new part will not cause failures when used in the system.
If the obsolete design is in VHSIC Hardware Description Language (VHDL) format, for example, the conversion may be easier. VHDL, and its associated support software permit easier simulations. Logic elements and interconnects are changed from the obsolete part and, should SFA or certification be required, the time before the new IC can be used will be extended.
U.S. Pat. No. 5,018,074 Griffith et al. discloses a method for making gate array masks in which a mask set for an existing set of gate array cells is converted to follow new design rules requiring non-uniform transformation of circuit components. The background of the invention provides that as fabrication processes are continually being improved to reduce geometry sizes, enhance device properties and lower productions costs, that many changes cannot be made to all components of the circuit. The patent takes advantage that for gate array cells, as compared to custom circuits, the masks/layout geometries differ only on the interconnect layers and the metal interconnect layers. All other layers, for example, field implant, diffusion and polysilicon are the same for every gate array cell.
Along these lines, U.S. Pat. No. 5,079,717 to Miwa also discloses a method for making a mask with pattern data which have been compaction processed, and wherein each level of a cell remains interconnected. Also relating to compaction, U.S. Pat. No. 5,493,509 to Matsumoto et al. discloses in its background section that compaction or spacing techniques involve shortening the distance between symbols as design rules permit to produce a high packing density layout. Compaction can be two-dimensional compaction, or one dimensional compaction where components are moved first in the x-direction and then in the y-direction. The one dimensional compaction may be a shear line method, a virtual grid method, and a constraint graph method, with the constraint graph method identified as the most widely used.
U.S. Pat. No. 5,416,722 to Edwards discloses computer aided design for compacting semiconductor circuit layouts to meet a specified set of design rules. The automated circuit layout compaction process begins by fracturing a specified circuit layout into a maximal set of trapezoids and then storing the resulting trapezoids in a connectivity data structure that denotes boundaries of each cell, and the cell adjacent to each boundary.
U.S. Pat. No. 4,803,636 to Nishiyama et al. discloses a circuit translator for logic circuits for automatically translating a logic circuit using a first type of technology, for example, CMOS to a logic circuit using a second type of device, for example I.sup.2 L. An input circuit inputs the elements of the circuit to be translated, a memory stores circuit translating rules, a group of optimizing rules, and a program for processing the translation, and an output device produces an intermediate result, such as on a graphic display. As noted, the translation rules become complex and large in number. A Boolean operation is described for translation rules in the same circuit technology.
U.S. Pat. No. 4,882,690 to Shinsha et al. discloses synthesizing an updated gate-level logic circuit which performs updated functions of current functions which, in turn, are performed by a current gate-level logic circuit so that a part is used in the updated circuit. The current circuit may include a modification to an original gate-level logic circuit synthesized by a computer for performing the current functions.
U.S. Pat. No. 5,553,274 to Liebmann discloses optical proximity correction for enhancing the fidelity of VLSI pattern transfer operations, and wherein a series of shrink, expand and subtraction operations are employed to fracture CAD pattern data into basic rectangles abutting at vertices in the original design. The thus defined rectangles are then classified as to their functional relevance based on their spatial relation to prior or subsequent CAD design levels. By shifting the edges of only the basic rectangles deemed relevant for improvement of the VLSI device performance, the generation of new vertices is minimized and effort is expended only on high value add portions of the circuit design.
Also relating to CAD tools for integrated circuit layout design, U.S. Pat. No. 5,461,577 to Shaw et al. discloses random logic circuitry laid out in a logic array that has a plurality of row and column locations. U.S. Pat. No. 5,517,421 to Jimbo et al. discloses a integrated circuit layout method wherein part data are revised along with the progress in semiconductor processes. When the content of one part or one element is updated to a new version, the influence of this update to a new version is readily determined based on the process data so that updating to a new version of the other parts can also be easily conducted based on the process data.
U.S. Pat. No. 5,308,798 to Brasen et al. also discloses computer aided design for integrated circuit layout. Similarly, U.S. Pat. No. 5,369,596 to Tokumaru discloses a computer aided design process also employing compaction. U.S. Pat. No. 5,537,648 to Liebmann et al. discloses a CAD system for generating phase shifted mask designs. U.S. Pat. No. 5,526,278 to Powell discloses a method and apparatus for converting field-programmable logic cell implementations into mask-programmable logic cell implementations, or into mask-programmable standard cell implementations. Unfortunately, specialized computer software can be relatively expensive and may not be suitable for a wide range of applications, particularly where it is desired to avoid the need for extensive testing or certification.